Side-channel Attack Standard Evaluation Board (SASEBO)

AIST > RCIS > Side-channel Attack Standard Evaluation Board (SASEBO) > CryptoLSI

Standard Cryptographic LSIs

This cryptographic LSI was fabricated with a 130-nm TSMC standard cell library. ISO/IEC 18033-3 standard block ciphers AES, Camellia, SEED, MISTY-1, CAST-128, a defact standard DES, and a public-key cipher RSA are supported. The key size for export version is limited as 56 bits for block ciphers and 512 bits for RSA.

Cryptographic LSI for SASEBO-R Specification Ver. 1.0 (English) (pdf 371KB)

Cryptographic LSI for SASEBO-R Specification Ver. 1.0 (Japanese) (pdf 418KB)

Two cryptographic LSIs fabricated with 90-nm and 130-nm TSMC standard cell libraries support elliptic curve cryptography as well as the ISO/IEC 18033-3 standard block ciphers and RSA. Seven AES circuits with side channel attack countermeasures are also integrated on the LISs.

Standard Cryptographic LSI Specification -with Side Channel Attack Counter Measures- Ver. 1.0 (pdf 6.95MB)

Standard Cryptographic LSI Specification -with Side Channel Attack Counter Measures- Ver. 1.0 (Japanese) (pdf 7.02MB)

This report provids experimental results of various power analysis attacks on the AES and RSA circuits, in which the cryptographic LSI on SASEBO-R and the Xilinx FPGA on SASEBO-G were used.

Power Analysis Attacks on SASEBO (pdf 11.93MB)

Power Analysis Attacks on SASEBO (Japanese) (pdf 11.57MB)